Poly-Si/SiO2 is a typical gate stack choice of MOSFETs, and has been applied in ULSIC manufacturing for long time. According to Moore's Law, the size of the poly-Si/SiO2 gate stack continuously reduces and the thickness of the gate oxide dielectric layer continuously decreases. However, in recent years, the thickness of the gate oxide dielectric layer begins to be subject to limitations of basic physical laws, challenging the thickness reduction prospect of the SiO2 gate oxide dielectric layer. Accordingly, for the sub-32 nm technology node, the industry has focused on high-k/metal gate stack which has decreased equivalent oxide thickness of the gate dielectric layer, improved device performance with high reliability close to the conventional gate stack. The high-k/metal gate technology has a significant contribution to the progress of the process technology on the sub-32 nm CMOS technology node.
Two main approaches have emerged in the high-k/metal gate technology: gate-first and gate-last. In the gate-first process, the metal gate is formed first and followed by S/D ion implantation and high temperature anneal. In the gate-last process, the metal gate is formed after S/D implantation and high temperature anneal.
Currently, the introduction of the gate-last process enables semiconductor chips to have lower power consumption, less current leakage, and higher reliability under high-frequency operation. Therefore, the gate-last process is believed to be a sustainable solution that will satisfy the technical requirement for sub-32 nm generation transistors and new transistors like FinFETs.
The gate last process is also called a damascene-gate process, which includes the following steps: performing a FEOL process to form a semiconductor device including an NMOS transistor and a PMOS transistor each with a polysilicon gate, depositing a pre-metal dielectric layer, exposing the polysilicon gates by CMP and removing the polysilicon gates by etching; depositing a high-k material and two metal gate electrodes; and removing the metal on the surface of the pre-metal dielectric layer by CMP. Finally, an NMOS transistor and a PMOS transistor each with a high-k/metal gate stack are formed and isolated from each other. Since the metal gates are not subject to the S/D high temperature anneal and different metal materials are deposited for the NMOS and PMOS transistors respectively, the threshold voltage of each transistor can be effectively controlled.
During the step of exposing the polysilicon gates mentioned above, materials above the polysilicon gates are removed by CMP. However, the CMP process has the following defects.
On one hand, since the polysilicon gates are covered by multiple dielectric layers such as a SiO2 dielectric layer, a Si3N4 high stress layer, and a doped pre-metal dielectric layer, the removal rate of SiO2, Si3N4 and polysilicon is difficult to control during the CMP process, which may cause surface defects and affect product yield.
On the other hand, the shear stress generated during the CMP process may affect the gate stacks, or even affect the carrier mobility that has been enhanced by strain engineering technology. Furthermore, high shear stress generated in the CMP process may also cause deformation of the polysilicon gates, which increases difficulties in the subsequent cleaning and deposition process steps.